Download Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current by P. van der Meer,A. van Staveren,Arthur H. M. van Roermund PDF

By P. van der Meer,A. van Staveren,Arthur H. M. van Roermund

1. 1 Power-dissipation tendencies in CMOS circuits Shrinking machine geometry, growing to be chip sector and elevated data-processing pace functionality are technological developments within the built-in circuit to magnify chip performance. Already in 1965 Gordon Moore anticipated that the entire variety of units on a chip might double each year till the Seventies and each 24 months within the Nineteen Eighties. This prediction is well known as "Moore's legislation" and finally culminated within the Semiconductor organization (SIA) expertise highway map [1]. The SIA highway map has been a consultant for the in­ dustry best them to persevered wafer and die dimension development, elevated transistor density and working frequencies, and illness density relief. to say a couple of numbers; the die dimension elevated 7% in keeping with 12 months, the smallest characteristic sizes lowered 30% and the working frequencies doubled each years. by reason of those tendencies either the variety of transistors and the ability dissi­ pation in line with unit zone raise. within the close to destiny the utmost strength dissipation in step with unit zone should be reached. Down-scaling of the availability voltage isn't just the simplest method to decrease energy dissipation in most cases it is also an important precondition to make sure equipment reliability by way of decreasing electric fields and equipment temperature, to avoid equipment degradation. A draw-back of this resolution is an elevated sign propa­ gation hold up, which ends up in a reduce data-processing velocity performance.

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